The European Patent Office considered a method for checking consistency and completeness of selection conditions to have at least some technical features. Here are the practical takeaways from the decision T 2330/13 (Checking selection conditions/SAP) of 9.5.2018 of Technical Board of Appeal 3.5.07:
This patent application relates to a method for efficiently checking the consistency and completeness of selection conditions for components of a configurable product. It can be used, for instance, for the purpose of assembling an automobile model from a catalogue of parts according to a particular set of design specifications, in order to ensure that the combinations of parts are correct. According to the description, the method is significantly faster than prior-art methods because it uses bit operations to evaluate the selection conditions.
Claim 1 (auxiliary request)
A computer implemented method for evaluation of selection conditions concerning variants of components in a configurable product during manufacturing of the configurable product, the selection conditions serving to prevent incompatible variants from being included in the configurable product, the method comprising:
receiving a plurality of selection conditions (S1, S2, S3) comprising logical operations defining permissible combinations of values of a finite set of characteristics of the product, wherein a variance space is defined by the set of all combinations of said values;
forming a bit matrix (300) containing information representing combinations of the values of the characteristics by encoding all possible combinations contained in the variance space into a matrix, wherein the bit matrix (300) comprises rows and columns, wherein for each value associated with a characteristic one of the rows is given, wherein for each combination of the values one of the columns is given;
splitting the bit matrix into a desired number of bit sub-matrices, wherein each bit sub-matrix corresponds to a variance subspace, the splitting comprising choosing a desired characteristic of the set of characteristics with a number of values that equals at least approximately the desired number of sub-matrices, and creating for every value of the desired characteristic a sub-matrix;
forming bit strings (s1, s2, s3) representing the selection conditions for all combinations in each variance subspace by applying the logical operations defined in the selection conditions to the bit sub-matrices, wherein the forming of the bit strings is performed by parallel processing, wherein each bit string representing the selection conditions has bits representing unique combinations of the values of the characteristics, wherein each of the permissible combinations of the values of the characteristics is expressed by a bit having the value logic “1” while all other bits in the bit strings representing the selection conditions have the value logic “0”;
receiving a plurality of restriction conditions (R1, R2) comprising logical operations defining forbidden combinations of the values of the finite set of the characteristics of the product;
forming bit strings (r1, r2) representing restriction conditions for all combinations in each variance subspace by applying the logical operations defined in the restriction conditions to the bit sub-matrices, wherein the forming of the bit strings is performed by parallel processing, wherein each bit string representing the restriction conditions has bits representing unique combinations of the values of the characteristics, wherein each of the restriction conditions is expressed by a bit having the value logic “1” for each forbidden combination while all other bits in the bit string have the value logic “0”;
determining inconsistent pairs of the selection conditions (S1, S2, S3) for each variance subspace by calculating inconsistency bit strings for pairs of the selection conditions (S1, S2, S3) and determining the inconsistent pairs of the selection conditions (S1, S2, S3) in a case when the inconsistency bit string of the pair of the selection conditions (S1, S2, S3) has at least one bit having a value logic “1”, wherein the inconsistency bit string of the pair of the selection conditions (S1, S2, S3) is formed by combining the corresponding bit strings representing the pair of selection conditions and a united bit string representing restriction conditions using logical AND operation, wherein the united string representing restriction conditions is formed by combining all bit strings representing restriction conditions using logical OR operation with subsequent applying logical NOT operation, wherein the determining of the inconsistent pairs of the selection conditions is performed by parallel processing; and
outputting the inconsistent pairs of the selection conditions to a user.
Is it patentable?
According to the Board, the claimed invention unquestionably contains elements of a mathematical / logical nature. In particular, claim 1 of the (amended) main request specifies that the received selection and restriction conditions comprise defined logical operations which are applied to bit sub-matrices in order to form bit strings and that bit strings are combined using logical AND, OR and NOT operations.
5.3 According to established case law, it is legitimate to have a mix of technical and non-technical features (i.e. features relating to non-inventions within the meaning of Article 52(2) EPC) in a claim, even if the non-technical features form a dominating part (T 641/00, OJ EPO 2003, 352, reasons 4). Inventive step in so-called mixed-type inventions is to be assessed by taking account of all those elements of the claimed subject-matter which contribute to its technical character (see T 641/00, supra, reasons 6 and 7). Features which would, taken in isolation, belong to the matters excluded from patentability under Article 52(2) EPC may nonetheless contribute to the technical character of the claimed invention (G 3/08, OJ EPO 2011, 10, reasons 12.2.2). However, purely non-technical elements which do not interact with the technical subject-matter of the claim for solving a technical problem are ignored (see T 154/04, OJ EPO 2008, 46, reasons 5(F)).
5.8 In summary, even though the task performed by claim 1 is of a non-technical nature (see point 5.6 above), the specific claimed bit (sub-)matrices, bit strings and steps of the method, especially those of splitting the bit matrix, forming bit strings representing the selection and restriction conditions and determining inconsistent pairs of selection conditions when performed by parallel processing, do contribute to the technical character of the invention and should be taken into account when assessing inventive step. Similar conclusions apply to the other claims of the main request.
Thus, the Board disagrees with the assessment of the examining division with respect to the technical charachter of a plurality of the claimed method steps. Moreover, said features were also found not to be notorious, and thereore have to be considered in the assessment of inventive step:
7. In the Board’s view, the features of claim 1 of the main request contributing to the technical character of the claimed subject-matter which were listed above are not notorious. Furthermore, it follows from the technical-character assessment above that the claimed method cannot be seen as corresponding to an obvious “human approach”, as argued in decision T 1954/08. Unlike the binary map in that case, the bit (sub-)matrices and bit strings of the present invention are not merely used to store “flagged information”, but instead play an important role in the processing steps which are specifically adapted to use those data structures for the efficient parallel evaluation of selection conditions in a computer.
Thus, the Board remitted the case back to the first instance examining division for re-examination of inventive step.
You can read the whole decision here: T 2330/13 (Checking selection conditions/SAP) of 9.5.2018